NAND flash memory is an example of a nonvolatile semiconductor memory device. A memory cell array of NAND flash memory includes memory cell units in which multiple memory cells are connected in series. A bit line and a source line are connected respectively to two ends of each memory cell unit via selection gate transistors. The control gates of the multiple memory cells inside each memory cell unit are connected respectively to different word lines.
In NAND flash memory, the data programming is performed by page unit, with the set of multiple memory cells connected to one word line being used as one page.
Thus, in NAND flash memory, the programming voltage is undesirably applied to the unselected memory cells to which the data is not to be programmed because the unselected memory cells share a word line with the selected memory cells to which the data is to be programmed.
Therefore, a self-boost is performed in which the channel potential of the unselected memory cells is increased due to capacitive coupling by setting the memory cell units including the unselected memory cells to be in the floating state and applying a programming voltage or a pass voltage to the word lines.
In such a case, misprogramming in which the data is programmed also to the unselected memory cells can be suppressed if the channel potential (the boost potential) of the unselected memory cells is increased by the self-boost to be sufficiently high.
However, the boost potential decreases due to the capacitive coupling with the adjacent memory cells. Therefore, when the dimensions between the memory cells decrease as downscaling progresses, there is a risk that the decrease of the boost potential may become pronounced because the capacitive coupling with the adjacent memory cells becomes large. As a result, there is a risk that misprogramming may increase.